Using `define in SV

These days i am hearing alot from a frnd of mine alot about the use of `define macro
he is a big fan of it and even i am finding it very useful once after using it.

The LRM gives an idea of how to use the macro and explains a how `,`` can be used inside a define macro.

but it just explains the basic stuff, there are far more useful ways in which you can use it.one such example is given below.


i have a task as shown



`define reg_0_location 16'h0001
`define reg_1_location 16'h0002
`define reg_2_location 16'h0003
`define reg_3_location 16'h0004
`define reg_4_location 16'h0005
`define reg_5_location 16'h0006
`define reg_6_location 16'h0007
`define reg_7_location 16'h0008

task generic_reg_write (reg_location,reg_value);



endtask


task register_config (input bit[2:0] reg_num)


case (reg_num)

3'h0: generic_reg_write (`reg_0_location,32'h1);
3'h1: generic_reg_write (`reg_1_location,32'h1);
3'h2: generic_reg_write (`reg_2_location,32'h1);
3'h3: generic_reg_write (`reg_3_location,32'h1);
3'h4: generic_reg_write (`reg_4_location,32'h1);
3'h5: generic_reg_write (`reg_5_location,32'h1);
3'h6: generic_reg_write (`reg_6_location,32'h1);
3'h7: generic_reg_write (`reg_7_location,32'h1);

endcase

endtask

The entire register_config task can be written using a single macro as shown


`define register_config (reg_num) \
generic_reg_write (`reg_``reg_num``_location,32'h1);


the above example is a simple one just for understanding we can actually pass one define to another define.

The following link gives more details of the same:
http://sandeep-vaniya.blogspot.com/2008/04/reusable-channel-using-define-macro.html