factory pattern

A very good post on factory pattern in java:
http://www.javacamp.org/designPattern/
http://download.oracle.com/docs/cd/E17409_01/javase/tutorial/java/concepts/interface.html

Using `define in SV

These days i am hearing alot from a frnd of mine alot about the use of `define macro
he is a big fan of it and even i am finding it very useful once after using it.

The LRM gives an idea of how to use the macro and explains a how `,`` can be used inside a define macro.

but it just explains the basic stuff, there are far more useful ways in which you can use it.one such example is given below.


i have a task as shown



`define reg_0_location 16'h0001
`define reg_1_location 16'h0002
`define reg_2_location 16'h0003
`define reg_3_location 16'h0004
`define reg_4_location 16'h0005
`define reg_5_location 16'h0006
`define reg_6_location 16'h0007
`define reg_7_location 16'h0008

task generic_reg_write (reg_location,reg_value);



endtask


task register_config (input bit[2:0] reg_num)


case (reg_num)

3'h0: generic_reg_write (`reg_0_location,32'h1);
3'h1: generic_reg_write (`reg_1_location,32'h1);
3'h2: generic_reg_write (`reg_2_location,32'h1);
3'h3: generic_reg_write (`reg_3_location,32'h1);
3'h4: generic_reg_write (`reg_4_location,32'h1);
3'h5: generic_reg_write (`reg_5_location,32'h1);
3'h6: generic_reg_write (`reg_6_location,32'h1);
3'h7: generic_reg_write (`reg_7_location,32'h1);

endcase

endtask

The entire register_config task can be written using a single macro as shown


`define register_config (reg_num) \
generic_reg_write (`reg_``reg_num``_location,32'h1);


the above example is a simple one just for understanding we can actually pass one define to another define.

The following link gives more details of the same:
http://sandeep-vaniya.blogspot.com/2008/04/reusable-channel-using-define-macro.html

Queue usage in System verilog

I am using a queue and loading/fetching data from it as if it is an array.The following examples shows how i actually did that

Ex:
Code snippet -1:
============
if i code as shown below

int arr_a[$];
arr_a[0] = 1;
arr_a[1] = 11;
//arr_a[2] = 2;
arr_a[3] = 22;

when i tried to print the array elements i am getting the following output
Results:
arr[0] = 1
arr[1] = 11
arr[2] = 0
arr[3] = 0

i reran the same code commenting index 0 element

int arr_a[$];
//arr_a[0] = 1;
arr_a[1] = 11;
arr_a[2] = 2;
arr_a[3] = 22;

Results:
arr[0] = 0
arr[1] = 0
arr[2] = 0
arr[3] = 0

so if any index is missing in assigning the variables all the indices above it fetches 0 when you pop.

explanation for the above behavior i got through a mail from a friend:

I ran a few tests and also looked at the 2009 standard. I believe that this is covered in the standard and is executing exactly as the standard specifies. To some degree, a gotcha is something that is allowed but not expected. In this case, this could be a gotcha, but it is not wrong.

As for "improper usage of SV construct", I suggest that the construct is working as defined. Please check out the paragraphs on reading and writing with invalid indexes at the end of section 7.10.1 in the 2009 standard. The results you got fall directly in line with the "invalid" read index. The simulator I ran my tests on gave me a warning (as the standard requires) when I tried to "skip" an index like you showed in code snippet #1.

I hope this helps.

`ifdef inside a define macro

i want a define to work depending on some input so i tried the following
`define def_a (input1,out)\
`ifdef COMMAND \
out= input1*3 \
`endif

Its properly compiling and the tc is going through fine.

some time back i read a post regarding #ifdef inside a #define in Cpp link for which is :
http://bytes.com/topic/c/answers/472611-possible-write-such-macro

where they mentioned
- Preprocessing directives can only span one line (the \ may hide
that but the above is only one source line) and there may be only
one preprocessing directive per line.
- Preprocessing directives start the respective line (but for
whitespace)
- Thus, you cannot generate preprocessing directives using
preprocessing directives; the language does not allow it.

I wanted to test above thing and tried similar thing in SV and to my surprise there are no issues and you can write `ifdef/`ifndef in a `define.

But one thing to make sure is no space after "\" in each line. if spaces are there it gives compilation error

Error:
not found match for `endif

So u can write such macros in SV.:)

A note on processes and fine grain control

In system verilog fork join block blocks the execution of the parent class until all the process in the fork join are completed. System verilog provides two more keywods join_any and join_none are provided which can be used when we wish to continue with the parent process execution eventhough the currently spawned threads are not completed. join_any waits until any one of the spawned processes to complete where as join_none wait for nothing.

A return statement within the context of a fork...join statement is illegal and results in a compilation error.

SV also provides key words wait fork and disable fork keywords to wait for all the processes are completed for the executing the code after the wait fork. disable fork is to disable all the processes that are active and also the decendents of the processes.

One more advantage of SV is we can do Fine-grain process control i.e.,we can wait,kill,suspend,resume and know the state of a perticular process for individual processes.

LRM states:

A process is a built-in class that allows one process to access and control another process once it has started.

class process;
enum state { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED };
static function process self();
function state status();
task kill();
task await();
task suspend();
task resume();
endclass

Objects of type process are created internally when processes are spawned. Users cannot create objects of type
process; attempts to call new shall not create a new process, and instead result in an error.

Call the 'self()' method of process class in the thread to be monitored and
then assign it to the process class object.

.status gives the status of the process.
= process::self()is like newing the object.
.kill will kill the process
.await will wait until that process is completed.


References:
SV LRM

following solvenet articles
https://solvnet.synopsys.com/retrieve/025657.html
https://solvnet.synopsys.com/retrieve/025656.html?otSearchResultSrc=advSearch&otSearchResultNumber=2&otPageNum=1

I got an interesting paper on different regions of a simulation time in SV.
They explained about every detail of all the different regions.
The system verilog is devided into 17 regions 8 of them are for execution of PLI code and rest are executing system verilog statements.
The nine regions are divided into 5 event region sets Preponed event region, Active event region, Observed, Reactive region set, Postponed event region.
Preponed event region: preponed region is executed once in a time slot and it will sample the values to be used in assertions. This region is read only and no assignments are done. the actual assignment can be in the postponed region of the previous time slot or the preponed region of current timeslot.
Active region: This region is to evaluate the blocking,non-blocking assignments in the module. This is having three sub regions in it. Active,Inactive, NBA. The active sub-region is for evaluating the RHS of non-blocking assihnments,executing all $finish,$display function and execution of blocking statements. Inactive region is for #0 delay statement scheduling. NBA sub region is for eveluating the non-blocking statements in the module.
Observed region: This region is for evaluating the concurrent assertions with the values sampled in preponed region.
Inactive region:This is similar to Active resion the only difference being in this region we will evaluate program block assignments.
Postponed event region: functionality of this region is for executing $strobe and $monitor regions and to collect functional coverage values of signals which are sampled using $strobe.

For further reading one can refer the following pdf:

http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf

well well its working
we had all functions(copy,psdisplay....) of VMM_DATA in all our vmm_data extension classes instead now we are using vmm macros (`vmm_data_member_scalar(variable,DO_ALL).....)and our TB is reduced to half its original size.
One can refer VMM standard library user guide version1.12 page A-148.
but i am not sure if i do it for classes using `vmm_data_member_handle(handleof a class,DO_ALL) do the handle i use should always be of a class which is derived from VMM_DATA?I have given a handle of a class which i defined which is not extension of VMM_DATA its giving null object access . Need to check on this.